The present invention relates to a semiconductor device, and more particularly, to semiconductor device with a gate stack structure.
A tungsten polysilicon gate electrode formed by stacking polysilicon and tungsten has a very low resistance which is about one fifth to one tenth times smaller than that of a polysilicon/tungsten silicide (Poly-Si/WSix) gate electrode formed by stacking polysilicon and tungsten silicide. Accordingly, the tungsten polysilicon gate electrode is necessary to fabricate sub-60 nm memory devices.
FIGS. 1A to 1C illustrate typical tungsten polysilicon gate stack structures. As shown in FIG. 1A, the tungsten polysilicon gate stack structure is formed by sequentially stacking a polysilicon layer 11, a tungsten nitride (WN) layer 12, and a tungsten (W) layer 13. The WN layer 12 serves as a diffusion barrier.
During a subsequent annealing process or a gate re-oxidation process, nitrogen in the WN layer 12 is decomposed to a non-uniform insulation layer such as SiNx and SiOxNy between the tungsten layer 13 and the polysilicon layer 11. The non-uniform insulation layer has a thickness ranging from about 2 nm to 3 nm. Accordingly, a device error such as a signal delay may be induced at an operation frequency of several hundreds of megahertz (MHz), and an operation voltage of 1.5 V or less. Recently, a thin tungsten silicide (WSix) or titanium (Ti) layer has been formed between the polysilicon layer 11 and the WN layer 12 as a diffusion barrier layer to prevent Si—N bonds from being formed between the tungsten layer 13 and the polysilicon layer 11.
As shown in FIG. 1B, if a tungsten silicide (WSix) layer 14 is formed between the polysilicon layer 11 and the WN layer 12, W—Si—N bonds are formed over the WSix layer 14 by nitrogen plasma used during the formation of the WN layer 12. It is well known that W—Si—N is a good diffusion barrier layer with a metallic characteristic.
As shown in FIG. 1C, if a titanium (Ti) layer 15 is formed between the polysilicon layer 11 and the WN layer 12, the nitrogen plasma transforms Ti of the titanium layer 15 to titanium nitride (TiN) in a reactive sputtering process during the formation of the WN layer 12. The TiN layer functions as a diffusion barrier layer. As a result, although the WN layer 12 is decompounded during a subsequent thermal process, the TiN prevents nitrogen from being diffused out towards the polysilicon layer 11 and thus, the formation of Si—N can be effectively reduced.
However, if the tungsten polysilicon gate is applied to a dual polysilicon gate [i.e., an N+-type polysilicon gate for an N-type metal oxide semiconductor field effect transistor (NMOSFET) and a P+-type polysilicon gate for a P-type metal oxide semiconductor field effect transistor (PMOSFET)], contact resistance between the tungsten layer and the P+-type polysilicon layer may be greatly increased if the WSix/WN diffusion barrier structure is used in the tungsten polysilicon gate. On the contrary, if the Ti/WN diffusion barrier structure is used in the tungsten polysilicon gate, the contact resistance between the tungsten layer and the P+-type polysilicon layer is low regardless of the polysilicon doping species.
In the case of P+-type polysilicon for the PMOSFET, a polysilicon depletion effect may be generated at an inversion state which is an actual operating mode. The generation of the polysilicon depletion effect may depend on the amount of boron remaining inside P+-type polysilicon.
The polysilicon depletion effect may be generated much more in the WSix/WN diffusion barrier structure than in the Ti/WN diffusion barrier structure. Consequently, the WSix/WN diffusion barrier structure may degrade the transistor properties. As a result, using the Ti/WN diffusion barrier structure is suggested because the Ti/WN diffusion barrier structure can provide low contact resistance between the tungsten layer and the polysilicon layer, and prevent the generation of P-type polysilicon depletion.
However, if the Ti/WN diffusion barrier structure is used, the sheet resistance (Rs) of W formed directly over the Ti/WN diffusion barrier structure may be increased by about 1.5 to 2 times. Accordingly, the increase in the sheet resistance (Rs) may affect the development of tungsten polysilicon gates in the future.